1. Field of the Invention
The invention relates to a mask pattern and, more particularly, to a mask pattern for defining a floating gate region.
2. Description of the Related Art
In flash memory fabrication, polymers are often generated on a source polysilicon layer and on an oxide layer during a word line trim etch step. These polymers will undesirably interfere with the subsequent processes, and deteriorate the reliability of a flash memory. The manufacturing process of a flash memory will be described with reference to the accompanying drawings.
First, silicon nitride/polysilicon/silicon nitride layers are formed, in which the polysilicon layer is a floating gate.
Next, a photolithography process is performed with the use of a mask pattern for defining a floating gate region, shown as mask pattern 11 in FIG. 1. Mask pattern 11 is used to define a floating gate region on the silicon nitride/polysilicon/silicon nitride layers.
The silicon nitride/polysilicon/silicon nitride layers are then etched, leaving only the silicon nitride/polysilicon/silicon nitride layers in the floating gate region.
Next, subsequent processes are performed to form a flash memory. First, first TEOS (tetraethylorthosilicate) oxide spacers 201, a source polysilicon layer 202, an oxide layer 203, word line poly-spacers 204, and second TEOS oxide spacers 205, are formed as shown in FIGS. 2A and 2B, in which FIG. 2A is a sectional view taken along the line A-Axe2x80x2 in corresponding FIG. 1, and FIG. 2B is a sectional view taken along the B-Bxe2x80x2 in corresponding FIG. 1.
Then, a second photolithography process is performed with the use of a word line trim mask pattern, shown as mask pattern 12 in FIG. 1, to form a photoresist layer 31 in a predetermined region. However, when all unwanted sections of polysilicon layer 202 are removed, and the alignment tolerance and the reduction in the effective photoresist region, caused by high exposure in the photolithography process, are taken in consideration, photoresist layer 31 is smaller than predetermined etching region 32 as shown in sectional view FIG. 3, which is taken along the line B-Bxe2x80x2 in corresponding FIG. 1.
Finally, a word line trim etch step is performed to remove unwanted sections of polysilicon layer 202 as shown in sectional views FIGS. 4A and 4B, in which FIG. 4A is taken along the line A-Axe2x80x2 in corresponding FIG. 1, and FIG. 4B is taken along the line B-Bxe2x80x2 in corresponding FIG. 1.
However, when a word line trim etch step is performed, since photoresist layer 31 is smaller than predetermined etching region 32, source polysilicon layer 202 is etched and damaged in this step, as shown in FIG. 4B. In addition, difficult to remove polymers are formed on second TEOS oxide spacers 205 and on source polysilicon layer 202 and undesirably interfere with the subsequent processes.
The invention is a mask pattern that prevents the source polysilicon layer from being etched and damaged in the word line trim etch step, and prevents the formation of difficult to remove polymers, which facilitates the subsequent manufacturing processes and improves the reliability of the flash memory.
The mask pattern of the invention includes a first region that is strip-shaped and has two long sides and two short sides, and two second regions that are strip-shaped with each region having two long sides and two short sides, in which the short sides of the second regions are shorter than the short sides of the first region, and the second regions extent in a lengthwise direction from the two short sides of the first region, respectively, with the short sides of the second regions adjacent to the short sides of the first region.
During the photolithography process in the manufacturing process of a flash memory, the mask pattern of the invention is used to define a floating gate region that is transferred to a semiconductor substrate. The manufacturing process includes an oxide spacer forming step and a word line trim etch step. When the oxide spacer forming step of the manufacturing process of the flash memory is performed, oxide spacers are not formed inside the trench, since the trench formed on the substrate corresponding to the second region has a high aspect ratio, and the trenches are instead filled.
The above and other objects, advantages, and features of the invention will become apparent from the following description with reference to the accompanying drawings.